A digital phase locked loop detects an oscillator phase and controls an oscillator frequency based on the detected phase information. The phase detection is performed in a manner that a phase component corresponding to an integer part (integer phase) is measured by a counter and a phase component corresponding to a fractional part (fractional phase) is detected by a time-to-digital converter (TDC).
The counter and the TDC operate at an oscillator frequency rate, thus consuming much power. A technique proposed to solve the problem uses a characteristic of an oscillator such that, as the oscillator comes closer to a phase-lock state, the change in oscillator phase difference becomes smaller. In the technique, the counter stops its operation at the moment close to the phase-lock state to reduce the power consumption of the phase locked loop.
However, when the counter stops its operation in the phase locked loop, a glitch is generated in a frequency or phase error signal. The glitch is different from true phase information and is generated to have a larger value than the TDC input range. Therefore, the glitch causes that the oscillator, which performs frequency control based on the TDC output signal, reduces its frequency stability so that the phase-lock state cannot be maintained.